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X5001
Data Sheet May 30, 2006 FN8125.1
CPU Supervisor
FEATURES * 200ms power-on reset delay * Low VCC detection and reset assertion --Five standard reset threshold voltages --Adjust low VCC reset threshold voltage using special programming sequence --Reset signal valid to VCC = 1V * Selectable nonvolatile watchdog timer --0.2, 0.6, 1.4 seconds --Off selection --Select settings through software * Long battery life with low power consumption --<50A max standby current, watchdog on --<1A max standby current, watchdog off * 2.7V to 5.5V operation * SPI mode 0 interface * Built-in inadvertent write protection --Power-up/power-down protection circuitry --Watchdog change latch * High reliability * Available packages --8 Ld TSSOP --8 Ld SOIC --8 Ld PDIP * Pb-free plus anneal available (RoHS compliant) BLOCK DIAGRAM
Watchdog Transition Detector SI SO SCK CS/WDI Data Register Command Decode & Control Logic
DESCRIPTION This device combines three popular functions, Poweron Reset, Watchdog Timer, and Supply Voltage Supervision in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. The watchdog timer provides an independent protection mechanism for microcontrollers. During a system failure, the device will respond with a RESET signal after a selectable time out interval. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The user's system is protected from low voltage conditions by the device's low VCC detection circuitry. When VCC falls below the minimum VCC trip point, the system is reset. RESET is asserted until VCC returns to proper operating levels and stabilizes. Five industry standard VTRIP thresholds are available, however, Intersil's unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. The device utilizes Intersil's proprietary Direct WriteTM cell for the watchdog timer control bits and the VTRIP storage element, providing a minimum endurance of 100,000 write cycles and a minimum data retention of 100 years.
Watchdog Timer
RESET
Reset & Watchdog Timebase
Power-on/ Low Voltage REset Generation
VCC
VTRIP
+ -
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X5001 Ordering Information
PART NUMBER X5001P-2.7 PART MARKING X5001P F VCC RANGE (V) 2.7 to 5.5 VTRIP RANGE 2.55 to 2.7 TEMP. RANGE (C) 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 2.85 to 3.0 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 4.5 to 5.5 4.25 to 4.5 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 PACKAGE 8 Ld PDIP 8 Ld PDIP (300 mil) (Pb-free) 8 Ld PDIP 8 Ld PDIP (300 mil) (Pb-free) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld TSSOP (4.4mm) 8 Ld TSSOP (4.4mm) (Pb-free) 8 Ld TSSOP (4.4mm) 8 Ld TSSOP (4.4mm) (Pb-free) 8 Ld PDIP 8 Ld PDIP (300 mil) (Pb-free) 8 Ld PDIP 8 Ld PDIP (300 mil) (Pb-free) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld TSSOP (4.4mm) 8 Ld TSSOP (4.4mm) (Pb-free) 8 Ld TSSOP (4.4mm) 8 Ld TSSOP (4.4mm) (Pb-free) 8 Ld PDIP 8 Ld PDIP (300 mil) (Pb-free) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) (Pb-free) PKG. DWG. # MDP0031 MDP0031 MDP0031 MDP0031 MDP0027 MDP0027 MDP0027 MDP0027 M8.173 M8.173 M8.173 M8.173 MDP0031 MDP0031 MDP0031 MDP0031 MDP0027 MDP0027 MDP0027 MDP0027 M8.173 M8.173 M8.173 M8.173 MDP0031 MDP0031 MDP0027 MDP0027 MDP0027 MDP0027
X5001PZ-2.7 (Note) X5001P ZF X5001PI-2.7 X5001P G
X5001PIZ-2.7 (Note) X5001P ZG X5001S8-2.7 X5001S8Z-2.7 (Note) X5001S8I-2.7 X5001S8IZ-2.7 (Note) X5001V8-2.7 X5001V8Z-2.7 (Note) X5001V8I-2.7 X5001V8IZ-2.7 (Note) X5001P-2.7A X5001PZ-2.7A (Note) X5001PI-2.7A X5001PIZ-2.7A (Note) X5001S8-2.7A X5001S8Z-2.7A (Note) X5001S8I-2.7A X5001S8IZ-2.7A (Note) X5001V8-2.7A X5001V8Z-2.7A (Note) X5001V8I-2.7A X5001V8IZ-2.7A (Note) X5001PI X5001PIZ (Note) X5001S8 X5001S8Z (Note) X5001S8I X5001S8IZ (Note) X5001 F X5001 ZF X5001 G X5001 ZG 501 F 5001 FZ 501 G 5001 GZ X5001P AN X5001P ZAN X5001P AP X5001P ZAP X5001 AN X5001 ZAN X5001 AP X5001 ZAP 501 AN 5001 ANZ 501 AP 5001 APZ X5001P I X5001P ZI X5001 X5001 Z X5001 I X5001 ZI
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X5001 Ordering Information (Continued)
PART NUMBER X5001V8 X5001V8Z (Note) X5001V8I X5001V8IZ (Note) X5001PI-4.5A X5001PIZ-4.5A (Note) X5001S8-4.5A X5001S8Z-4.5A (Note) X5001S8I-4.5A X5001S8IZ-4.5A (Note) X5001V8-4.5A X5001V8Z-4.5A (Note) X5001V8I-4.5A X5001V8IZ-4.5A (Note) PART MARKING 501 5001 Z 501 I 5001 IZ X5001P AM X5001P ZAM X5001 AL X5001 ZAL X5001 AM X5001 ZAM 501 AL 5001 ALZ 501 AM 5001 AMZ 4.5 to 5.5 4.5 to 4.75 VCC RANGE (V) 4.5 to 5.5 VTRIP RANGE 4.25 to 4.5 TEMP. RANGE (C) 0 to 70 0 to 70 -40 to 85 -40 to 85 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 PACKAGE 8 Ld TSSOP (4.4mm) 8 Ld TSSOP (4.4mm) (Pb-free) 8 Ld TSSOP (4.4mm) 8 Ld TSSOP (4.4mm) (Pb-free) 8 Ld PDIP 8 Ld PDIP (300 mil) (Pb-free) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld TSSOP (4.4mm) 8 Ld TSSOP (4.4mm) (Pb-free) 8 Ld TSSOP (4.4mm) 8 Ld TSSOP (4.4mm) (Pb-free) PKG. DWG. # M8.173 M8.173 M8.173 M8.173 MDP0031 MDP0031 MDP0027 MDP0027 MDP0027 MDP0027 M8.173 M8.173 M8.173 M8.173
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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PIN CONFIGURATION
8 Ld TSSOP RESET VCC CS/WDI SO 1 2 3 4 X5001 8 7 6 5 SCK SI VSS VPE CS/WDI SO VPE VSS 8 Ld SOIC/PDIP 1 2 3 4 X5001 8 7 6 5 VCC RESET SCK SI
PIN DESCRIPTION Pin (SOIC/PDIP)
1
Pin TSSOP
1
Name
CS/WDI
Function
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW transition on CS is required. Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET/RESET going active. Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out. Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first. Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or watchdog bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin. VTRIP Program Enable. When VPE is LOW, the VTRIP point is fixed at the last valid programmed level. To readjust the VTRIP level, requires that the VPE pin be pulled to a high voltage (15-18V). Ground Supply Voltage Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 200ms. RESET goes active if the watchdog timer is enabled and CS/WDI remains either HIGH or LOW longer than the selectable watchdog time out period. A falling edge of CS/WDI will reset the watchdog timer. RESET goes active on power-up at 1V and remains active for 200ms after the power supply stabilizes. No internal connections
2 5
2 8
SO SI
6
9
SCK
3
6
VPE
4 8 7
7 14 13
VSS VCC RESET
3-5,10-12
NC
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X5001
PRINCIPLES OF OPERATION Power-on Reset Application of power to the X5001 activates a poweron reset circuit. This circuit goes active at 1V and pulls the RESET/RESET pin active. This signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When VCC exceeds the device VTRIP value for 200ms (nominal) the circuit releases RESET, allowing the processor to begin executing code. Low Voltage Monitoring During operation, the X5001 monitors the VCC level and asserts RESET if supply voltage falls below a preset minimum VTRIP. The RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms. Watchdog Timer The watchdog timer circuit monitors the microprocessor activity by monitoring the WDI input. The microprocessor must toggle the CS/WDI pin periodically to prevent a RESET signal. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog time out period. The state of two nonvolatile control bits in the watchdog register determine the watchdog timer period. Vcc Threshold Reset Procedure The X5001 is shipped with a standard VCC threshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or if higher precision is needed in the VTRIP value, the X5001 threshold may be adjusted. The procedure is described in the following sections, and requires the application of a high voltage control signal. Setting the VTRIP Voltage This procedure is used to set the VTRIP to a higher voltage value. For example, if the current VTRIP is 4.4V and the new VTRIP is 4.6V, this procedure will directly make the change. If the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value. To set the new VTRIP voltage, apply the desired VTRIP threshold voltage to the VCC pin and tie the WPE pin to the programming voltage VP. Then a VTRIP programming command sequence is sent to the device over the SPI interface. This VTRIP programming sequence consists of pulling CS LOW, then clocking in data 03h, 00h and 01h. This is followed by bringing CS HIGH then LOW and clocking in data 02h, 00h, and 01h (in order) and bringing CS HIGH. This initiates the VTRIP programming sequence. VP is brought LOW to end the operation. Resetting the VTRIP Voltage This procedure is used to set the VTRIP to a "native" voltage level. For example, if the current VTRIP is 4.4V and the new VTRIP must be 4.0V, then the VTRIP must be reset. When VTRIP is reset, the new VTRIP is something less than 1.7V. This procedure must be used to set the voltage to a lower value. To reset the VTRIP voltage, apply greater than 3V to the VCC pin and tie the WPE pin to the programming voltage VP. Then a VTRIP command sequence is sent to the device over the SPI interface. This VTRIP programming sequence consists of pulling CS LOW, then clocking in data 03h, 00h and 01h. This is followed by bringing CS HIGH then LOW and clocking in data 02h, 00h, and 03h (in order) and bringing CS HIGH. This initiates the VTRIP programming sequence. VP is brought LOW to end the operation.
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Figure 1. Sample VTRIP Reset Circuit
4.7K Adjust VTRIP Adj. Run 1 2 3 4 8 7 X5001 6 5 RESET C
VP
SCK SI SO CS
Figure 2. Set VTRIP Level Sequence (VCC = desired VTRIP value)
VPE VPE = 15-18V
CS 0 SCK 16 Bits SI 03h 0001h 02h 0001h 16 Bits 1 23 4 56 78 9 10 20 21 22 23 0 1 23 4 56 78 9 10 20 21 22 23
Figure 3. Reset VTRIP Level Sequence (VCC > 3V)
VPE VPE = 15-18V
CS 0 SCK 16 Bits SI 03h 0001h 02h 0003h 1 23 4 56 78 9 10 20 21 22 23 0 1 23 4 56 78 9 10 20 21 22 23
16 BITS Bits
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Figure 4. VTRIP Programming Sequence
VTRIP Programming
Execute Reset VTRIP Sequence
Set VCC = VCC Applied = Desired VTRIP
New VCC Applied = Old VCC Applied + Error
Execute Set VTRIP Sequence
New VCC Applied = Old VCC Applied - Error
Apply 5V to VCC
Execute Reset VTRIP Sequence
Decrement VCC (VCC = VCC - 50mV)
NO
RESET pin goes active? YES
Error < 0
Measured VTRIP Desired VTRIP Error = 0 DONE
Error > 0
SPI INTERFACE The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. The device monitors the CS/WDI line and asserts RESET output if there is no activity within user selectable timeout period. The device also monitors the VCC supply and asserts the RESET if VCC falls below a preset minimum (VTRIP). The device contains an 8-bit watchdog timer register to control the watchdog time out period. The current settings are accessed via the SI and SO pins.
All instructions (Table 1) and data are transferred MSB first. Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off.
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Watchdog Timer Register 7
0
Read Watchdog Timer Register Operation 3
WD0
6
0
5
0
4
WD1
2
0
1
0
0
0
Watchdog Timer Control Bits The watchdog timer control bits, WD0 and WD1, select the watchdog time out period. These nonvolatile bits are programmed with the set watchdog timer (SWDT) instruction. Watchdog Control Bits WD1
0 0 1 1
If there is not a nonvolatile write in progress, the read watchdog timer instruction returns the setting of the watchdog timer control bits. The other bits are reserved and will return'0' when read. See Figure 3. If a nonvolatile write is in progress, the read watchdog timer register Instruction returns a HIGH on SO. When the nonvolatile write cycle is completed, a separate read watchdog timer instruction should be used to determine the current status of the watchdog control bits. RESET Operation The RESET (X5001) output is designed to go LOW whenever VCC has dropped below the minimum trip point and/or the watchdog timer has reached its programmable time out limit. The RESET output is an open drain output and requires a pull-up resistor. Operational Notes The device powers-up in the following state: - The device is in the low power standby state. - A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. - SO pin is high impedance. - The watchdog change latch is reset. - The RESET signal is active for tPURST. Data Protection The following circuitry has been included to prevent inadvertent writes: - A EWDC instruction must be issued to enable a change to the watchdog timeout setting. - CS must come HIGH at the proper clock count in order to implement the requested changes to the watchdog timeout setting.
WD0
0 1 0 1
Watchdog Time Out (Typical)
1.4 seconds 600 milliseconds 200 milliseconds disabled
Write Watchdog Register Operation Changing the watchdog timer register is a two step process. First, the change must be enabled by setting the watchdog change latch (see below). This instruction is followed by the set watchdog timer (SWDT) instruction, which includes the data to be written (Figure 5). Data bits 3 and 4 contain the watchdog settings and data bits 0, 1, 2, 5, 6 and 7 must be "0". Watchdog Change Latch The watchdog change latch must be SET before a Write watchdog timer operation is initiated. The Enable Watchdog Change (EWDC) instruction will set the latch and the Disable Watchdog Change (DWDC) instruction will reset the latch (Figure 6). This latch is automatically reset upon a power-up condition and after the completion of a valid nonvolatile write cycle.
Table 1. Instruction Set Definition Instruction Format
0000 0110 0000 0100 0000 0001
Instruction Name and Operation
EWDC: Enable Watchdog Change Operation DWDC: Disable Watchdog Change Operation SWDT: Set Watchdog Timer control bits: Instruction followed by contents of register: 000(WD1) (WD0)000 See Watchdog Timer Settings and Figure 7. RWDT: Read Watchdog Timer Control Bits
0000 0101
Note:
Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first.
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Figure 5. Read Watchdog Timer Setting
CS
0 SCK
1
2
3
4
5
6
7
... ...
W D 1 W D 0
RWDT Instruction SI
SO
...
Figure 6. Enable Watchdog Change/Disable Watchdog Change Sequence
CS
0 SCK
1
2
3
4
5
6
7
Instruction (1 Byte) SI High Impedance
SO
Figure 7. Write Watchdog Timer Sequence
CS 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction SI 6 5
Data Byte 4 3
SO
High Impedance
WW DD 10
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Figure 8. Read Nonvolatile Status (Option 1) (Used to determine end of Watchdog Timer store operation)
CS
0 SCK
1
2
3
4
5
6
7
RWDT Instruction SI Nonvolatile Write in Progress
SO
SO HIGH During 1st Bit While in the Nonvolatile Write Cycle
Figure 9. Read Nonvolatile Status (Option 2) (Used to determine end of Watchdog Timer store operation)
CS
0 SCK
1
2
3
4
5
6
7
RWDT Instruction SI Nonvolatile Write in Progress SO SO HIGH During Nonvolatile Write Cycle
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ABSOLUTE MAXIMUM RATINGS Temperature under bias ................... -65C to +135C Storage temperature ........................ -65C to +150C Voltage on any pin with respect to VSS ...................................... -1.0V to +7V D.C. output current ............................................... 5mA Lead temperature (soldering, 10s) .................... 300C COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this datasheet) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS Temperature Commercial Min. 0C Max.
+70C
Voltage Option -1.8 -2.7 or -2.7A -4.5 or -4.5A
Note: PT= Package, Temperature
Supply Voltage Limits 1.8V to 3.6V 2.7V to 5.5V 4.5V to 5.5V
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Symbol
ICC1 ICC2 ISB1 ISB2 ISB3 ILI ILO VIL(1) VIH(1) VOL1 VOL2 VOL3 VOH1 VOH2 VOH3 VOLRS
Parameter
VCC write current (Active) VCC read current (Active) VCC standby current WDT=OFF VCC standby current WDT=ON VCC standby current WDT=ON Input leakage current Output leakage current Input LOW voltage Input HIGH voltage Output LOW voltage Output LOW voltage Output LOW voltage Output HIGH voltage Output HIGH voltage Output HIGH voltage Reset output LOW voltage
Min.
Limits Typ
Max. 5
0.4 1 50 20
Unit
mA mA A A A A A V V V V V V V V
Test Conditions
SCK = VCC x 0.1/VCC x 0.9 @ 5MHz, SO = Open SCK = VCC x 0.1/VCC x 0.9 @ 5MHz, SO = Open CS = VCC, VIN = VSS or VCC, VCC = 5.5V CS = VCC, VIN = VSS or VCC, VCC = 5.5V CS = VCC, VIN = VSS or VCC, VCC = 3.6V VIN = VSS to VCC VOUT = VSS to VCC
0.1 0.1 -0.5 VCC x 0.7
10 10 VCC x 0.3 VCC + 0.5 0.4 0.4 0.4
VCC > 3.3V, IOL = 2.1mA 2V < VCC < 3.3V, IOL = 1mA VCC 2V, IOL = 0.5mA VCC > 3.3V, IOH = -1.0mA 2V < VCC 3.3V, IOH = -0.4mA VCC 2V, IOH = -0.25mA IOL = 1mA
VCC-0.8 VCC-0.4 VCC-0.2 0.4
V
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POWER-UP TIMING Symbol
tPUR
(2) (2)
Parameter
Power-up to read operation Power-up to write operation
Min.
Max.
1 5
Unit
ms ms
tPUW
CAPACITANCE (TA = +25C, f = 1MHz, VCC = 5V) Symbol
COUT(2) CIN
(2)
Test
Output capacitance (SO, RESET) Input capacitance (SCK, SI, CS)
Max.
8 6
Unit
pF pF
Conditions
VOUT = 0V VIN = 0V
Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
3V 5V 3.3k RESET 100pF 30pF
A.C. TEST CONDITIONS
Input pulse levels Input rise and fall times Input and output timing level VCC x 0.1 to VCC x 0.9 10ns VCC x0.5
1.64k Output 1.64k
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Data Input Timing 1.8V-3.6V SymboL
fSCK tCYC tLEAD tLAG tWH tWL tSU tH tRI(3) tFI(3) tCS tWC
(4)
2.7V-5.5V Min.
0 500 200 200 200 200 50 50 2 2 2 2 150 10 10
Parameter
Clock frequency Cycle time CS lead time CS lag time Clock HIGH time Clock LOW time Data setup time Data hold time Input rise time Input fall time CS deselect time Write cycle time
Min.
0 1000 400 400 400 400 100 100
Max.
1
Max.
2
Unit
MHz ns ns ns ns ns ns ns s s ns ms
250
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Data Output Timing 1.8V-3.6V Symbol
fSCK tDIS tV tHO tRO tFO
(3) (3)
2.7V-5.5V Min.
0
Parameter
Clock frequency Output disable time Output valid from clock low Output hold time Output rise time Output fall time
Min.
0
Max.
1 400 400
Max.
2 200 200
Unit
MHz ns ns ns ns ns
0 300 300
0 150 150
Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
Figure 10. Data Output Timing
CS tCYC SCK tV SO MSB Out MSB-1 Out tHO tWL LSB Out tDIS tWH tLAG
SI
ADDR LSB IN
Figure 11. Data Input Timing
tCS CS tLEAD SCK tSU SI MSB In tH tRI tFI LSB In tLAG
SO
High Impedance
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SYMBOL TABLE
WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
Figure 12. Power-Up and Power-Down Timing
VTRIP VCC 0 Volts tR RESET (X5001) tPURST tPURST tF tRPD VTRIP
RESET Output Timing Symbol
VTRIP
Parameter
Reset trip point voltage, X5001PT-4.5A Reset trip point voltage, X5001PT-4.5 Reset trip point voltage, X5001PT-2.7A Reset trip point voltage, X5001PT-2.7 Reset trip point voltage, X5001PT-1.8 Power-up reset timeout VCC detect to reset/output VCC fall time VCC rise time Reset valid VCC
Min.
4.50 4.25 2.85 2.55 1.70 100 0.1 0.1 1
Typ.
4.63 4.38 2.92 2.63 1.75 200
Max.
4.75 4.50 3.00 2.70 1.80 280 500
Unit
V
tPURST tRPD(5) tF(5) tR(5) VRVALID
Note:
ms ns ns ns V
(5) This parameter is periodically sampled and not 100% tested. PT = Package, Temperature
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Figure 13. CS vs. RESET Timing
CS tCST RESET tWDO tRST tWDO tRST
RESET Output Timing Symbol
tWDO
Parameter
Watchdog timeout period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 CS pulse width to reset the watchdog Reset Timeout
Min.
100 450 1 400 100
Typ.
200 600 1.4 200
Max.
300 800 2 300
Unit
ms ms sec ns ms
tCST tRST
VTRIP Programming Timing Diagram
VCC (VTRIP) VP VPE tVPS CS tPCS tVPH tVPO VTRIP tTSU tTHD
tRP
SCK
SI 03h 0001h 02h 0001h or 0003h
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VTRIP Programming Parameters Parameter
tVPS tVPH tPCS tTSU tTHD tWC tVPO tRP VP VTRAN Vta1 Vta2 Vtr Vtv
Description
VTRIP program enable voltage setup time VTRIP program enable voltage hold time VTRIP programming CS inactive time VTRIP setup time VTRIP hold (stable) time VTRIP write cycle time VTRIP program enable voltage Off time (between successive adjustments) VTRIP program recovery period (between successive adjustments) Programming voltage VTRIP programmed voltage range Initial VTRIP program voltage accuracy (VCC applied-VTRIP) (programmed at 25C) Subsequent VTRIP program voltage accuracy [(VCC applied-Vta1)-VTRIP. Programmed at 25C.] VTRIP program voltage repeatability (Successive program operations. Programmed at 25C.) VTRIP program variation after programming (0-75C). (programmed at 25C)
Min.
1 1 1 1 10
Max.
Unit
s s s s ms
10 0 10 15 1.7 -0.1 -25 -25 -25 18 5.0 +0.4 +25 +25 +25
ms s ms V V V mV mV mV
VTRIP programming parameters are periodically sampled and are not 100% tested.
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VCC Supply Current vs. Temperature (ISB)
20 18 Reset (seconds)
tWDO vs. Voltage/Temperature (WD1, 0 = 1, 1)
1.85
Watchdog Timer On (VCC = 5V) 17 14 Isb (A) 11
1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.7 3.1 Voltage 4.5 90C 25C -40C
15 Watchdog Timer On (VCC = 3V)
Watchdog Timer Off (VCC = 3V, 5V) 0.55 0.35 -40C 25C Temp (c)
1.0 90C
VTRIP vs. Temperature (programmed at 25C)
5.025 5.000 4.975 3.525 Voltage 3.500 3.475 2.525 2.500 2.475 0 25 Temperature 85 VTRIP = 2.5V VTRIP = 3.5V VTRIP = 5V
tWDO vs. Voltage/Temperature (WD1, 0 = 1, 0)
0.85 0.80 Reset (seconds) 0.75 25C 0.70 0.65 0.60 1.7 3.1 Voltage 4.5 90C
-40C
tPURST vs. Temperature
280 275 270 265 Time (ms) 260 255 250 245 240 235 -40 25 Degrees C 90
tWDO vs. Voltage/Temperature (WD1, 0 0 = 0, 1)
0.30 0.29 0.28 0.27 0.26 0.25 0.24 0.23 0.22 0.21 0.20 1.7
Reset (seconds)
25C
-40C
90C
3.1 Voltage
4.5
17
FN8125.1 May 30, 2006
X5001 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. L 2/01
18
FN8125.1 May 30, 2006
X5001 Plastic Dual-In-Line Packages (PDIP)
D E N PIN #1 INDEX
SEATING PLANE L e b
A2
A c
E1
A1 NOTE 5
eA eB
1
2 b2
N/2
MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL A A1 A2 b b2 c D E E1 e eA eB L N PDIP8 0.210 0.015 0.130 0.018 0.060 0.010 0.375 0.310 0.250 0.100 0.300 0.345 0.125 8 PDIP14 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 14 PDIP16 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 16 PDIP18 0.210 0.015 0.130 0.018 0.060 0.010 0.890 0.310 0.250 0.100 0.300 0.345 0.125 18 PDIP20 0.210 0.015 0.130 0.018 0.060 0.010 1.020 0.310 0.250 0.100 0.300 0.345 0.125 20 TOLERANCE MAX MIN 0.005 0.002 +0.010/-0.015 +0.004/-0.002 0.010 +0.015/-0.010 0.005 Basic Basic 0.025 0.010 Reference Rev. B 2/99 NOTES: 1. Plastic or metal protrusions of 0.010" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. 2 1 NOTES
19
FN8125.1 May 30, 2006
X5001 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM
M8.173
8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.116 0.169 0.246 0.0177 8 0o 8o 0o MAX 0.047 0.006 0.051 0.0118 0.0079 0.120 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 2.95 4.30 6.25 0.45 8 8o MAX 1.20 0.15 1.05 0.30 0.20 3.05 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 1 12/00
e
b 0.10(0.004) M C AM BS
A1 0.10(0.004)
A2 c
E1 e E L N
0.026 BSC
0.65 BSC
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 20
FN8125.1 May 30, 2006

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